1. Field of the Invention
The invention relates to a converting device, more particularly to an N-bit digital-to-analog converting device.
2. Description of the Related Art
Referring to FIG. 1, in C. H. Lin and K. Bult, “A 10-b, 500-MSample/s CMOS DAC in 0.6=2,” IEEE J. Solid-State Circuits, vol. 33, no. 12, 1948-1958, December 1998, there is disclosed a conventional N-bit digital-to-analog converting device that is adapted for receiving an N-bit binary digital signal D[k] and a clock signal (CK), and that is operable for outputting, within each cycle of the clock signal (CK), an analog voltage (vo) related to the digital signal D[k]. The N-bit digital-to-analog converting device includes a decoder 1 and a converting module 2.
When the N-bit binary digital signal D[k] is in an equally-weighted segmenting mode, the decoder 1 is adapted for receiving the N-bit binary digital signal D[k], and is operable to convert the N-bit binary digital signal D[k] received thereby into a thermometer code (T) represented by 2N bits.
The converting module 2 includes a plurality (2N) of converters 21 and a load 22.
Each of the converters 21 is adapted to receive the clock signal (CK), is coupled electrically to the decoder 1 for receiving therefrom a corresponding one of the 2N bits that represent the thermometer code (T), is operable to generate a current with a current flow direction dependent on logic level of the corresponding one of the 2N bits, and includes a latch circuit (L), a current source (I), a first switch (S1), and a second switch (S2). Operations among the latch circuit (L), the current source (I), the first switch (S1), and the second switch (S2) are described in the aforementioned publication, and hence will not be detailed hereinafter.
The load 22, which includes two resistors, is coupled electrically to the converters 21 and generates the analog voltage (vo) based on a summation of the currents generated by the converters 21.
Shown in FIG. 2 is a timing diagram of the conventional N-bit digital-to-analog converting device, in which D[1]-D[4] are the values of the digital signal D[k] at four different time points, and the analog voltage (vo) is shown to vary according to the digital signal D[k]. Moreover, a non-ideal effect associated with switching of the first switch (S1) and the second switch (S2) causes a spurious wave to be present in the analog voltage (vo), which leads to a spurious free dynamic range (SFDR) degradation. Frequencies of switching of the first switch (S1) and the second switch (S2) are in a negative relation to the SFDR.
FIG. 3 shows a plot of measured output obtained for the conventional N-bit digital-to-analog converting device in a configuration where the clock signal (CK) has a sampling rate of 1.6 GS/s and the digital signal D[k] has an input frequency of 731 MHz. It is apparent that the SFDR is reduced to 43 dB as a result of an increase in the third harmonic component attributed to the non-ideal effect associated with switching of the first and second switches (S1, S2).